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AMD-V: AMD64 virtualization extension

Date and Time

Wednesday, November 18, 2009 from 6:30 pm to 9:00 pm

Location

MIT Building E-51, Room 325

Presenter

Shankar Viswan, - shankar.viswan gmail com

Summary

Shankar discusses AMD's hardware virtualization

Abstract

Shankar Viswanathan will describe the details of the hardware virtualization features implemented in AMD64 processors. Named AMD-V (formerly codenamed "Pacifica"), these architecture extensions greatly reduce the overhead involved in running multiple guest operating systems on top of the Virtual Machine Monitor (VMM). Shankar will discuss how AMD-V handles tasks such as saving and restoring OS state, how memory and paging is handled and give a brief overview of how IO peripherals are virtualized. A rough knowledge of the x86 architecture is beneficial, but not a prerequisite for this talk.

About Shankar Viswan

Shankar Viswanathan has been involved in high performance microprocessor design for almost 10 years, last 5 years of which have been at AMD. His first project at AMD was the Pacifica extensions for the AMD Opteron, Athlon64 and Turion64 processors. He is currently working on the next generation "Fusion" microprocessor at AMD.

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